The present invention relates to an automobile speed control system for maintaining automobile speed at a desired speed and more particularly to a set, memory and cancel circuit arranged in an automobile speed control system for maintaining a constant speed.
In such controls, the actual speed of an automobile is detected at a pulse frequency and the actual speed signal is obtained by the analog voltage level which is in proporation to the pulse frequency. A memory circuit sets or memorizes the actual automobile speed signal at the moment that a desired speed switch is closed. This memorized automobile speed signal is then used as a reference signal by the comparator circuit and on the basis of the difference between the reference signal and the actual automobile speed, the automobile speed control system controls the movement of the throttle valve into a position at which the difference is zero.
In prior art, speed control devices for automobiles, a frequency-voltage converting circuit FVC and a memory circuit, or voltage holding circuit, FSH, are utilized as shown in FIG. 1. A constant voltage V.sub.cc regulated by Zener diode ZD is supplied to these circuits and the frequency-voltage converting circuit FVC receives an actual speed signal from a reed switch 3 which opens and closes repeatedly in synchronism with the rotation of a magnet 2 which is rotated at the same speed as the speedometer cable of an automobile. The frequency-voltage converting circuit FVC converts the actual speed signal into a voltage pulsating between the constant voltage level and the ground level and supplies the voltage to transistor Q.sub.a through resistor R.sub.a and capacitor C.sub.a which absorb the high frequency pulsation caused by chattering of the reed segment in the reed switch 3. The transistor Q.sub.a turns ON and OFF in correspondence with the actual speed signal so that the voltage level at the connection point between resistor R.sub.v and R.sub.c changes. According to the changes in the voltage level, capacitor C.sub.b is charged through the resistor R.sub.b and discharged through the resistor R.sub.c. The base and emitter of transitor Q.sub.b are biased to the same voltage level through the diodes D.sub.a and D.sub.b respectively, and therefore, transistor Q.sub.b is OFF. When the voltage level at the connection point between resistors R.sub.b and R.sub.c is at a high level H, the emitter of transistor Q.sub.b is biased higher than the base thereof for the time determined by the time constant of resistor R.sub.b and capacitor C.sub.b so that the transistor Q.sub.b turns ON. The voltage at the collector of the transistor Q.sub.b is normally at the low level and when the transistor Q.sub.b is turned ON, the voltage at the collector changes to the high level so the voltage at the collector of transistor Q.sub.b is at the high level for the time determined by the time constant of the resistence of resistor R.sub.b and the capacity of capacitor C.sub.b in each frequency cycle of the actual speed signal. The pulse signal which has a constant pulse width caused by transistor Q.sub.b is connected to an integrating circuit which is comprised of resistor R.sub.d and capacitor C.sub.c so that the voltage level of capcitor C.sub.c corresponds to the repetition rate of the pulse which is proportional to the actual speed signal and indicates the actual speed voltage signal through the transistor Q.sub.c.
The memory circuit SH memorizes the actual speed voltage signal which indicates the desired speed of the automobile. The memory circuit SH includes a memory capacitor C.sub.d, field effect transistors (FET) Q.sub.d, Q.sub.e, and resistor R.sub.e. The source of FET Q.sub.d receives either the constant voltage V.sub.cc through resistor R.sub.e or is connected to ground through resistor R.sub.f. In the state where the desired speed set signal is not supplied, the gate of FET Q.sub.d is at the low level whereby transistor Q.sub.f is in its ON state so that current cannot flow from the drain to the source. When the desired speed set signal is supplied, the voltage level of the gate of FET Q.sub.d switches to the high level whereby transistor Q.sub.f turns OFF so that current can flow from the drain to the source. One terminal of the capacitor C.sub.d is connected to the connection point between the resistor R.sub.e and resistor R.sub.f which indicate a reference voltage level V.sub.r and another terminal of the capacitor C.sub.d is connected to an actual speed voltage signal V.sub.v. Therefore, the voltage difference V.sub.v -V.sub.r is charged in the capacitor C.sub.d. By taking off the desired set signal, FET Q.sub.d turns OFF because of FET Q.sub.e being a high impedence element, a terminal of capacitor C.sub.d which is connected to FET Q.sub.d is in the state of floating, so the electric charge of capacitor C.sub.d is held at the moment the desired speed set signal is taken off and therefore a differential voltage V of capacitor C.sub.d is held at the level of V.sub.v -V.sub.r. Thus, the voltage level V.sub.v plus V is applied to the gate of FET Q.sub.e and is supplied from the source of FET Q.sub.e as the memory voltage signal V.sub.m. Thereafter, as the actual speed of the automobile rises, the memory voltage signal V.sub.m rises correspondingly and if the actual speed of the automobile decreases, the memory voltage V.sub.m falls correspondingly. By comparing this memory voltage signal V.sub.m with the constant voltage level V.sub.x, the difference signal between the actual automobile speed and the desired automobile speed is supplied and an automobile speed control system will maintain the actual automobile speed constant at the desired speed.
However, in this type of automobile speed control system, when the power source is cut off momentarily by a faulty connector, memory voltage memorized in capacitor C.sub.d is changed and the automobile speed control system will make an error. FIG. 2 is a graph showing a time chart which indicates the level change of each signal when the power source voltage V.sub.b is cut off temporarily. Referring to FIG. 1 and FIG. 2, when the voltage V.sub.b drops to zero, the charge memorized in capacitor C.sub.e is discharged so that the voltage V.sub.cc decreases exponentially and the voltages V.sub.r and V.sub.v decrease also. The terminal voltage V.sub.c of capacitor C.sub.c in an integral circuit decreases, but because resistors R.sub.d and R.sub.g connected to capcitor C.sub.c have a high value, transistor Q.sub.c is biased oppositely and the voltage V.sub.c decreases more slowly than the voltages V.sub.cc, V.sub.r, and V.sub.v. When the voltage V.sub.r decreases to a certain level at T.sub.1, FET Q.sub.d turns ON, the voltage V.sub.v -V.sub.r is applied to capcitor C.sub.d. When the voltage V.sub.B returns to a fixed voltage at T.sub.3, the voltages V.sub.cc, V.sub.r, V.sub.v, and V.sub.c will begin to increase. If the voltage V.sub.r is over a certain voltage at the time T.sub.4, FET Q.sub.d turns OFF and the voltage V.sub.v1 -V.sub.r1 applied to capacitor C.sub.d is memorized in capacitor C.sub.d. However, the voltage level of V.sub.v1 -V.sub.r1 differs from the voltage level of V.sub.V0 -V.sub.r0 which is memorized before the momentary voltage cut off. In practice, by cutting off the momentary voltage, the voltage memorized in capacitor C.sub.d is changed into a voltage which increases the automobile speed. For example, if a desired speed is set at 60 km/h, by cutting off the voltage momentarily it is possible that the speed will increase to 80 km/h. Therefore, it is dangerous to have an automobile run faster than the driver intends. While a driver can easily notice a change in speed due to a momentary cut off of voltage when a automobile is supposed to be running at a constant speed, it is very hard for the driver to notice the change of speed if the momentary voltage cutoff occurs at a time when the speed control system is not in operation. If the momentary voltage cutoff occurs during this time, the automobile will run at a higher speed than desired when the speed control system resumes control of the automobile speed.